Increased miniaturization of components, and greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases.
Semiconductor package structures continue to advance toward miniaturization and thinning to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large scale IC (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner, and the package configurations that house and protect them are required to be made smaller and thinner as well.
Many conventional semiconductor die (or “chip”) packages are of the type where a semiconductor die is molded into a package with a resin, such as an epoxy molding compound. The packages have a lead frame whose out leads are projected from the package body, to provide a path for signal transfer between the die and external devices. Other conventional package configurations have contact terminals or pads formed directly on the surface of the package.
Such a conventional semiconductor package is fabricated through the following processes: a die-bonding process (mounting the semiconductor die onto the paddle of a lead frame), a wire-bonding process (electrically connecting the semiconductor die on the paddle to inner leads using lead frame wires), a molding process (encapsulating a predetermined portion of the assembly, containing the die, inner leads and lead frame wires, with an epoxy resin to form a package body), and a trimming process (completing each assembly as individual, independent packages).
The semiconductor packages, thus manufactured, are then mounted by matching and soldering the external leads or contact pads thereof to a matching pattern on a circuit board, to thereby enable power and signal input/output (“I/O”) operations between the semiconductor devices in the packages and the circuit board.
An exemplary semiconductor package, well known in the electronics industry, is the quad flat no-lead package (“QFN”). QFN packages typically comprise a lead frame, such as a conductive sheet stamped and etched, with a semiconductor die having a multitude of bond pads mounted to the top side of the lead frame. Wire bonds electrically connect the bond pads, of the semiconductor die, to a series of conductive lead fingers on the top side of the lead frame. Typically, the semiconductor die and the wire bonds are encapsulated within a molding compound.
In order to reduce manufacturing costs, the electronics industry is increasing the usage of QFN packages. In the manufacturing process, many obstacles must be overcome to deliver extremely small packages in high volume. One such obstacle is mold flash covering some of the inner lead contacts and preventing a reliable printed circuit board connection. This situation may be caused by debris on the mold bottom chase under the lead fingers or the clamping pressure on one end of a half etched lead causes the other end to lift. Another possibility is that the lead fingers may be bent or lifted prior to the molding step. The result of these issues is that the finished package may be missing some of the contact pads necessary to connect it to the printed circuit board.
Still thinner, smaller, and lighter package designs and mounting/connecting configurations have been adopted in response to continuing requirements for further miniaturization. At the same time, users are demanding semiconductor packages that are more reliable under increasingly severe operating conditions.
Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved yield, and thinner height for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.